Von Neumann Architecture:
• Von Neumann Model is the most common architecture representation of a computer system.
• In 1945, it was published by John von Neumann.
• The Von Neumann architecture includes Arithmetic & Logic Unit (ALU), Control Unit (CU), Memory Unit, Inputs/Outputs (I/O) and Registers.
• John von Neumann’s idea is based on holding data and programs in read-write Random Access Memory (RAM) and then transferring it to the Memory Unit and processor i.e. the idea of a stored program.
• Before the introduction of stored programs, data and programmed instructions were stored separately.
• Von Neumann’s idea to treat programmed instructions as data has made many programming tools possible including assembler and compiler.
• Figure (i) shows a basic Von Neumann's architecture representation that shows the connection between processor and memory with buses.
• Figure (ii) is a more detailed representation of a Von Neumann architecture and introduces the concept of registers and addresses.
Figure i Basic Von Neumann's Architecture
Figure ii Detailed Von Neumann's Architecture
Central Processing Unit (CPU):
• The CPU is responsible for executing instructions.
• It includes the Control Unit, Arithmetic and Logic Unit, and various registers.
1. Arithmetic and Logic Unit:
• It responsible for carrying out the logic operations (OR, AND, NOT, XOR, etc.) and arithmetic operations (add, multiplication, subtract, etc.).
2. Control Unit:
• It is responsible for controlling the operations of the Arithmetic and Logic Unit (ALU), Memory Unit and I/O devices.
• It tells the devices, how to respond to programmed instructions after interpreting the instructions from the memory unit.
• In the CPU, there are high-speed storage areas known as registers.
• Before data is processed, it first must be stored in a register.
• In Figure (ii), you can see various types of register. The details of some registers are as under:
• It is also known as the Fetch-Decode-Execute cycle.
• It is the basic operations (instructions) cycle of a computer system.
• During this cycle, programmed instruction is retried from the memory and then the required actions are performed as per the instructions.
• While the computer system is ON, the fetch-decode-execute cycle is repeated continuously.
Steps of the Cycle:
1. PC (Program Counter) contains the next instruction address.
2. The address in PC is loaded in MAR (Memory Address Register).
3. Lookup for MAR and copy instructions data into MDR (Memory Data Register).
4. Copy data from MDR to CIR (Current Instruction Register).
5. Increment the Program Counter by 1.
6. Decode the instructions data available in CIR.
7. Execute the instruction.
8. Reset (repeat from step 1).
Figure iii Fetch Execute Cycle
(Credit: Computer Science by D. Watson & H. Williams)
• It allows the transmission of data from one part to another part of a computer system.
• It provides a connection from internal components to memory and processor.
• A typical CPU is comprised of the following three types of buses:
• It is responsible for transmitting the data addresses between memory and processor.
• It does not transmit the data, only the addresses.
• It is responsible for transmitting the data between the memory unit, processor and the I/O devices.
• It is responsible for transmitting the control commands/signals from the CPU in order to coordinate and control all activities within the computer system.
• It also carries the status signal from other devices.